{"id":341318,"date":"2016-12-26T12:27:55","date_gmt":"2016-12-26T20:27:55","guid":{"rendered":"https:\/\/cm-edgetun.pages.dev\/en-us\/research\/?post_type=msr-research-item&#038;p=341318"},"modified":"2018-10-16T21:02:56","modified_gmt":"2018-10-17T04:02:56","slug":"practical-approach-exploiting-coarse-grained-pipeline-parallelism-c-programs","status":"publish","type":"msr-research-item","link":"https:\/\/cm-edgetun.pages.dev\/en-us\/research\/publication\/practical-approach-exploiting-coarse-grained-pipeline-parallelism-c-programs\/","title":{"rendered":"A Practical Approach to Exploiting Coarse-Grained Pipeline Parallelism in C Programs"},"content":{"rendered":"<p>The emergence of multicore processors has heightened the need for effective parallel programming practices. In addition to writing new parallel programs, the next generation of programmers will be faced with the overwhelming task of migrating decades\u2019 worth of legacy C code into a\u00a0 parallel representation. Addressing this problem requires a toolset of parallel programming primitives that can broadly apply to both new and existing programs. While tools such\u00a0 as threads and OpenMP allow programmers to express task and data parallelism, support for pipeline parallelism is distinctly lacking.<\/p>\n<p>In this paper, we offer a new and pragmatic approach to leveraging coarse-grained pipeline parallelism in C programs. We target the domain of streaming applications, such as audio, video, and digital signal processing, which exhibit regular flows of data. To exploit pipeline parallelism,\u00a0 we equip the programmer with a simple set of annotations (indicating pipeline boundaries) and a dynamic analysis that tracks all communication across those boundaries. Our analysis outputs a stream graph of the application as well as a set of macros for parallelizing the program and communicating the data needed. We apply our methodology to six case studies, including MPEG-2 decoding, MP3 decoding, GMTI radar processing, and three SPEC benchmarks. Our analysis extracts a useful block diagram for each application, and the parallelized versions offer a 2.78x mean speedup on a 4-core machine.<\/p>\n","protected":false},"excerpt":{"rendered":"<p>The emergence of multicore processors has heightened the need for effective parallel programming practices. In addition to writing new parallel programs, the next generation of programmers will be faced with the overwhelming task of migrating decades\u2019 worth of legacy C code into a\u00a0 parallel representation. Addressing this problem requires a toolset of parallel programming primitives [&hellip;]<\/p>\n","protected":false},"featured_media":0,"template":"","meta":{"msr-url-field":"","msr-podcast-episode":"","msrModifiedDate":"","msrModifiedDateEnabled":false,"ep_exclude_from_search":false,"_classifai_error":"","msr-author-ordering":null,"msr_publishername":"","msr_publisher_other":"","msr_booktitle":"","msr_chapter":"","msr_edition":"William Thies, Vikram Chandrasekhar, and Saman Amarasinghe. IEEE\/ACM International Symposium on Microarchitecture (MICRO 2007). Chicago, IL","msr_editors":"","msr_how_published":"","msr_isbn":"","msr_issue":"","msr_journal":"","msr_number":"","msr_organization":"","msr_pages_string":"","msr_page_range_start":"","msr_page_range_end":"","msr_series":"","msr_volume":"","msr_copyright":"","msr_conference_name":"William Thies, Vikram Chandrasekhar, and Saman Amarasinghe. IEEE\/ACM International Symposium on Microarchitecture (MICRO 2007). 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