The constant need for faster and more energy\u2010efficient processors has been stimulating the development of new architectures, such as low\u2010power many\u2010core architectures. Researchers aiming to study these architectures are challenged by peculiar characteristics of some components such as networks\u2010on\u2010chip and lack of specific tools to evaluate their performance. In this context, the goal of this paper is to present a benchmark suite to evaluate state\u2010of\u2010the\u2010art low\u2010power many\u2010core architectures such as the Kalray MPPA\u2010256 low\u2010power processor, which features 256 compute cores in a single chip. The benchmark was designed and used to highlight important aspects and details that need to be considered when developing parallel applications for emerging low\u2010power many\u2010core architectures. As a result, this paper demonstrates that the benchmark offers a diverse suite of programs with regard to parallel patterns, job types, communication intensity, and task load strategies suitable for a broad understanding of performance and energy consumption of MPPA\u2010256 and upcoming many\u2010core architectures. Copyright \u00a9 2016 John Wiley & Sons, Ltd.<\/p>\n","protected":false},"excerpt":{"rendered":"
The constant need for faster and more energy\u2010efficient processors has been stimulating the development of new architectures, such as low\u2010power many\u2010core architectures. Researchers aiming to study these architectures are challenged by peculiar characteristics of some components such as networks\u2010on\u2010chip and lack of specific tools to evaluate their performance. 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